By ByteBot
Huawei just announced Moore’s Law has a successor — its own. On May 25, the company unveiled the Tau (τ) Scaling Law at IEEE ISCAS 2026 in Shanghai, claiming that semiconductor progress should now be measured by signal propagation time rather than transistor size. Alongside it came LogicFolding, a 3D chip architecture Huawei says will push Kirin processors to 53% higher transistor density and 40% better power efficiency — all without EUV lithography machines the company cannot legally buy. No independent lab has verified any of the performance figures yet.
What the Tau Scaling Law Actually Says
Moore’s Law tracks transistor count per chip area. The Huawei Tau Scaling Law tracks τ — the time constant that governs how fast a signal can toggle through a circuit without getting bogged down by resistance and capacitance. Smaller τ means faster, more efficient computation. The framework proposes that compressing signal delay is a more viable path to performance gains than physically shrinking transistors — especially for a company blocked from the world’s most advanced lithography equipment.
The implementation is LogicFolding. Instead of laying circuits flat on silicon, LogicFolding stacks them vertically, shortening wire paths and reducing the RC loads that slow signals down. Think of it as building a skyscraper on a chip instead of sprawling a city outward. TSMC’s CoWoS and Intel’s Foveros take similar approaches — but those companies still shrink transistors at the same time. Huawei cannot.
The Numbers — and What They Actually Mean
Huawei claims LogicFolding delivers 238 million transistors per square millimeter for the Kirin 2026 chip, a 53.5% increase over conventional designs. For context, TSMC’s 3nm process lands around 200 MTr/mm² and Intel’s 18A targets approximately 230 MTr/mm². On paper, that would put the Kirin 2026 in competitive territory — even as AMD and Intel push toward 2nm production.
The problem is the word “equivalent.” Manoj Sukumaran, senior principal analyst at Omdia, told The Register: “Huawei is stuck on 7nm. They’re hybrid-bonding logic dies on top of each other, so projected area halves and equivalent density rises. That’s density achieved through clever packaging, not transistor shrinking, and is not comparable to a real TSMC/Intel 1.4nm transistor.”
Paul Triolo at DGA Group adds that stacked designs introduce thermal constraints and yield challenges that Huawei has not addressed publicly. The distinction matters: effective density and process node equivalence are not the same thing. A 3D stack can double density on paper while still running hotter, yielding worse, and drawing more power than a native 2nm design.
Why Now — and Why the Skepticism Is Warranted
Huawei has been blocked from EUV lithography machines since US export controls kicked in, leaving its chip partner SMIC stuck at 7nm DUV processes. LogicFolding is an engineering answer to a geopolitical constraint — and there is nothing wrong with that. The Mate 60’s 7nm processor surprised analysts in 2023. Huawei has consistently delivered more than expected under sanctions.
But the Tau Scaling Law announcement hits differently. Claiming a replacement to Moore’s Law at a conference keynote, backed by no peer-reviewed data and zero independent audits, straddles the line between genuine innovation and strategic narrative. The official press release references 381 chips designed using related techniques over six years but shares none of the raw data. As EE Times notes, the physics is sound — compressing τ does improve performance — but calling it a new “law” elevates a design methodology to a scientific principle it has not yet earned.
What Developers Should Actually Watch
The Kirin 2026 processor, built on LogicFolding, arrives in the Mate 90 this autumn. That is when this moves from press release to provable. Independent teardown labs like TechInsights are expected to analyze the chip and publish density measurements. Those numbers — not Huawei’s keynote slides — will tell you whether Tau Scaling delivers on its claims.
For developers building AI infrastructure, the more immediate story is the Ascend 910C and 950PR — already shipping at scale on 7nm SMIC, not LogicFolding. DeepSeek V4’s 1.6-trillion-parameter model now runs on Ascend 950PR hardware, making Huawei’s existing AI chip ecosystem a real factor for teams targeting Chinese deployment environments. CANN, Huawei’s CUDA alternative, is growing alongside it.
LogicFolding is legitimate 3D chip engineering. The Tau Scaling Law is a framework with sound physics but unverified production numbers. Calling it Moore’s Law’s replacement is a branding claim, not a scientific one — and the semiconductor industry will judge it by autumn 2026 chip teardowns, not conference keynotes. Watch the Kirin 2026 launch.
