By ByteBot
Python core developer Stan Ulbrych announced this week that CPython officially recognizes RISC-V — specifically the riscv64-unknown-linux-gnu platform triplet — as a Tier 3 supported platform. The Python Steering Council approved the designation on August 20, it was formally added to PEP 11 on August 22, and the public announcement dropped August 24. RISC-V is now the only fully open instruction set architecture in CPython’s official support list — no proprietary license, no royalties, just an open standard anyone can implement.
What “Officially Supported” Actually Means
Tier 3 is an entry-level designation — and that’s not a knock. PEP 11 defines three tiers with very different guarantees. Tier 1 platforms (x86_64, ARM64, Windows) gate every CPython release on CI passing. Break one, the release stops. Tier 2 has a 24-hour fix-or-revert SLA with multiple core developer owners. Tier 3 is different: one core developer is responsible, a buildbot must exist, but failures do not block releases and there’s no fix timeline.
As HN commenter yjftsjthsd-h put it bluntly: “Tier 3 is still a caveat. Still allowed to break without blocking anything or being fixed as a priority.” That’s the honest read. RISC-V now has a formal place in Python’s governance, not a guarantee that every CPython release will run cleanly on your board. Other Tier 3 platforms include Android, iOS, FreeBSD, armv7l, and s390x — so RISC-V is in established company, just not yet the inner circle.
RISC-V: Python’s First Open ISA
Here’s what makes this more than a routine platform addition: every other platform in CPython’s support tiers — x86, ARM, WASM — carries proprietary or licensed architecture roots. RISC-V is an open standard governed by RISC-V International. No company owns the ISA. Anyone can design a chip without a license agreement. That’s why RISC-V’s market is projected to quadruple by 2032, and why the hardware is finally reaching enterprise grade.
The timing isn’t accidental. In the same week as the CPython announcement, SiFive launched BigSky — the first enterprise rack-mountable RISC-V server — and The Register reported it’s already selling out in limited quantities. Ubuntu 26.04 LTS and RHEL 10 both support RISC-V deployments. NVIDIA is porting CUDA to the architecture. Python joining this moment, even at Tier 3, signals that the open hardware movement has cleared the “experimental” label.
Related: RISE RISC-V Runners: Free GitHub Actions CI (2026) — the free CI infrastructure that will power CPython’s RISC-V buildbot integration.
What the Ecosystem Actually Supports Right Now
CPython is the interpreter — but the package ecosystem is the real blocker. The good news is that pip 24.1+ already understands riscv64 manylinux wheels (the manylinux_2_39_riscv64 tag arrived July 2025). The less-good news: most packages on main PyPI still don’t ship riscv64 binaries. You’ll need the RISE project’s supplementary package index for popular libraries.
PyTorch 2.13.0 landed on riscv64 just last week via the RISE Python Wheels project, with wheels for CPython 3.12 through 3.14t. Test results on native Scaleway EM-RV1 hardware: 165,591 passed out of 212,038 test cases — 99.998% success. However, there are gaps: no RVV vectorization means PyTorch falls back to scalar code, and FBGEMM/QNNPACK quantization backends aren’t available yet. NumPy and pandas have riscv64 wheels through RISE; the long tail of PyPI packages still requires building from source.
The interpreter works. Your dependencies might not — check before you commit.
The Path to Tier 2
Stan Ulbrych’s announcement is explicit about where this goes next. The goal is Tier 2, which requires proving CI reliability over time. CPython is integrating with the RISE RISC-V Runners — the free GitHub Actions service launched in March 2026 — to get faster feedback than the existing buildbots. HN commenter phire noted that Tier 2 eligibility “primarily requires proving the CI infrastructure is reliable (which takes time at tier 3).” Ulbrych also flagged interest in architecture-specific RISC-V optimizations once the platform stabilizes.
Community members with RISC-V hardware can help accelerate this: run CPython’s test suite on your boards, report breakage on bugs.python.org, and contribute to the RISE Python Wheels project to expand binary coverage. The faster the CI track record builds, the faster Tier 2 arrives.
Key Takeaways
- RISC-V (
riscv64-unknown-linux-gnu) is now a Tier 3 CPython platform — official recognition, but best-effort; failures don’t block releases - This is the first open instruction set architecture in PEP 11, a significant milestone for the open hardware movement
- The interpreter runs; PyPI binary coverage requires pip 24.1+ and the RISE supplementary index for most popular packages
- PyTorch 2.13.0, NumPy, and pandas are available via RISE — expect performance gaps on compute workloads until RVV vectorization ships
- Tier 2 is the goal; RISE RISC-V Runners CI integration is the path, and community contributions on real hardware accelerate it
