By ByteBot
Nvidia announced at Hot Chips 2026 this week that CUDA — the GPU compute platform powering most of the world’s AI workloads — will officially support RISC-V CPUs, making the open-source instruction set the third supported host architecture alongside x86 and ARM. Nvidia is partnering with SiFive, whose forthcoming high-core-count server chip will demo the integration at the conference. With 6 million CUDA developers and hundreds of millions of GPU-accelerated machines running on the framework, this is a significant architectural shift — but the fine print matters considerably more than the headline.
The Requirements Are the Story
Nvidia’s RISC-V CUDA support isn’t a blanket extension to all RISC-V hardware. The company has published a strict baseline: chips must implement the RVA23 CPU profile (which mandates vector extensions, hypervisor support, and a long list of ISA extensions), comply with the RISC-V Server SoC specification (adding RAS features, a security processor, and manageability requirements), and meet the RISC-V Server Platform specification for UEFI/ACPI boot. On top of that, PCIe coherency and PCIe peer-to-peer are mandatory — both for correct data synchronization and multi-GPU configurations.
The practical consequence: no current consumer RISC-V hardware qualifies. Your VisionFive 2, Milk-V Pioneer, or StarFive board will not run CUDA. Chester Lam’s Hot Chips 2026 analysis at Chips and Cheese put it plainly — deployments will “target server systems rather than single board computers.” ACPI support on RISC-V, while formally ratified in the BRS spec last year, is still years from widespread production implementation. The same adoption curve ARM endured. The same wait applies here.
The Enterprise and China Driver Behind NVIDIA CUDA RISC-V
The strategic rationale for Nvidia becomes clear when you look at who benefits from this move. China accounts for roughly 50% of global RISC-V shipments and has mandated RISC-V integration in critical government infrastructure — finance, energy, telecommunications. Chinese AI labs need GPU compute, and building domestically-designed RISC-V server CPUs provides a path to pairing them with Nvidia GPUs where export licenses allow. That’s a specific market, and it’s a large one.
The second driver is NVLink Fusion. In January 2026, SiFive announced it will integrate Nvidia’s NVLink Fusion into its next-generation data center chip designs. NVLink Fusion lets third-party CPU designers license Nvidia’s C2C interconnect, enabling coherent CPU-GPU links that share a memory address space — far more efficient than PCIe alone for AI inference pipelines where data movement is the bottleneck. SiFive’s RISC-V chip with NVLink Fusion won’t ship before 2027, but when it does, it gives AI data centers a non-Intel, non-AMD CPU option with near-native GPU bandwidth. RISC-V International confirmed the CUDA extension positions RISC-V as a full third-tier architecture alongside x86 and ARM in Nvidia’s ecosystem.
Related: DeepSeek Harness: Free MIT Runtime, 140K Stars, One Catch — another open-source AI runtime making waves with different trade-offs.
The Other Path: RISC-V AI Without CUDA
While Nvidia expands its CUDA moat into RISC-V territory, Tenstorrent has been quietly shipping an alternative that doesn’t require Nvidia at all. The Galaxy Blackhole compute server — integrating RISC-V CPUs, tensor processors, GDDR6 memory, and 400G networking in a single box — went GA on April 28, 2026. Its software stack, TT-Metalium, is MIT-licensed and supports PyTorch, JAX, and ONNX out of the box. Tom’s Hardware noted the broader significance of CUDA’s RISC-V extension, but Tenstorrent’s stack shows the alternative trajectory taking shape simultaneously.
Qualcomm has reportedly pursued acquisition talks valuing Tenstorrent at up to $14 billion, which, if it closes, would put a major incumbent squarely behind an anti-Nvidia, open RISC-V AI compute stack. CUDA on RISC-V extends Nvidia’s ecosystem. TT-Metalium sidesteps it entirely. For AI infrastructure teams making long-horizon bets, these are genuinely different architectures with different dependency risks.
What Developers Should Do With This
For 2026, the honest timeline is: nothing changes. SiFive’s RISC-V server chips with NVLink Fusion are a 2027-at-earliest story. ACPI stack maturity on RISC-V platforms is a multi-year effort. The software side is moving faster — Ubuntu 26.04 LTS is the first long-term support release with full RVA23 profile support, which helps — but shipping hardware is the constraint.
Enterprise AI infra teams planning three-year roadmaps should note this as a 2027–2028 decision point: RISC-V CPUs may become viable for GPU-attached server racks, particularly for organizations wanting to avoid ARM licensing or Intel supply-chain dependencies. Teams wanting RISC-V AI compute now have a working option in Tenstorrent Galaxy Blackhole. And CUDA developers on x86 or ARM can ignore this until 2027 without missing anything actionable.
Key Takeaways
- Nvidia’s CUDA now officially supports RISC-V as a host architecture — but requires RVA23, ACPI, PCIe coherency, and server-class silicon; no consumer RISC-V hardware qualifies today
- The primary drivers are China’s domestic AI server market (roughly 50% of global RISC-V shipments) and hyperscalers designing custom silicon outside Intel, AMD, and ARM supply chains
- SiFive’s NVLink Fusion integration means RISC-V CPUs could eventually attach to Nvidia GPUs with near-native bandwidth — but not before 2027
- Tenstorrent’s Galaxy Blackhole (GA since April 2026) offers RISC-V AI compute today via MIT-licensed TT-Metalium, with no CUDA dependency required
- CUDA on RISC-V expands Nvidia’s ecosystem reach — it does not break Nvidia’s moat
